 技術摘要： |
本發明是有關一種電路及其應用方法，特別是一種增加鎖頻範圍之注入式除頻及/或抑制諧波之電路及其應用方法，透過降低電感之品質因子大小，使得相位顫動發生頻率及相位雜訊增加，導致因震盪所輸出之訊號頻率於頻譜上會產生間歇性的漂移(縮短或加長)，進而達到增加鎖頻範圍；並可利用兩電晶體之閘極串聯一屏障電阻構成一偶次諧波抑制模組，當輸入訊號通過該偶次諧波抑制模組而產生交叉耦合後，進而達到增加鎖頻範圍及諧波抑制之功效。
The invention includes a harmonic suppression circuit, an injection-locked frequency divider circuit (ILFD) and associated methods. The harmonic suppression circuit comprises a source voltage, two suppression modules, two input terminals, two smoothed output terminals and a ground. The ILFD comprises a ground, an input transistor, an input terminal, two divider legs, two output terminals and a source voltage. The associated method to improve harmonic suppression comprises acts of synthesizing differential-phase signals and simultaneously suppressing second harmonics of in-phase signals. The method to extent an ILFD's locking range comprises acts of decreasing quality factor while keeping resonance frequency constant.
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聯繫方式 |
| 聯絡人：
研發處產學合作總中心 |
電話：
(02)3366-9949 |
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| 地 址：
10617臺北市大安區羅斯福路四段1號 禮賢樓六樓608室 |
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