GLOBAL ELIMINATION ALGORITHM FOR MOTION ESTIMATION AND THE HARDWARE ARCHITECTURE THEREOF
  ‧ 專利名稱
  ‧ 專利證書號
  ‧ 專利權人 國立臺灣大學
  ‧ 專利國家
    (申請日)
美國 (2002/06/27)
  ‧ 發明人 陳良基, 黃毓文, 簡韶逸,
 
技術摘要:
A global elimination algorithm for motion estimation and the hardware architecture thereof that can efficiently remove the braches in the data flow, so that the data flow is smoothened and is more adapted for hardware implementation. Because the processing time for each motion vector is fixed, preliminary prediction can be eliminated. The elimination ratio of the search locations will not be varied with time change and thus can be increased. The global elimination algorithm can produce a search result of high accuracy that is identical to that of a full-search block matching algorithm. The peak signal-to-noise ratio of global elimination algorithm is at times better than that of full-search block matching algorithm. Compared with other architectures based on the full-search block matching algorithm, the hardware architecture of the present invention can provide a best computational capability for each logic gate, while the power consumption of logic gates is minimum under the same throughput of motion vector.




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