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 電子工程學研究所 -
張耀文
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專業技術：
奈米積體電路實體設計, 電子設計自動化, 積體電路可製造性設計, 生醫晶片設計自動化 |
| 研究介紹 |
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◎研究領域 |
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Electronic Design Automation (with an emphasis on physical design for nanometer IC's)
Design for Manufacturing/Reliability
Design Automation for Analog Circuits
Board, Package, and Chip Co-design
Field-programmable Gate Arrays (FPGAs)
Combinatorial Optimization |
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專利 |
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T.-C. Chen, Y.-W. Chang, and C.-C. Lin, “V-Shaped Multilevel Full-Chip Gridless Routing,” US 2007/0256045, 2010
T.-C. Chen, P.-H. Yu, Y.-W. Chang, F.-J. Lin, and D. Liu, “Method of packing-based macro placement and semiconductor chip using the same,” US 2007/0157146, Dec. 2009
T.-C. Chen, Y.-W. Chang, and C.-C. Lin,, “Multilevel IC Floorplanner,” US Patent 7,603,640, Oct. 2009 |
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| 專利授權區 |
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加權平均線長模型
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本發明係一種用以產生積體電路中複數個元件佈局之電腦實現法，藉由使用一加權平均線長模型估算總線長以達成...... more
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| 可交易技術 |
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專利行銷平台