技術摘要: |
本發明係提供一種內容定址記憶體,可接受一輸入資料、一樣式資料及一資料時脈信號,並輸出一命中信號及一位址信號,其包括:複數個內容定址記憶單元,每一內容定址記憶單元接受該輸入資料、該資料時脈信號且彼此串接,並輸出一比對結果信號;以及一編碼器,分別耦接至該等內容定址記憶單元之比對結果信號,且可根據該等比對結果信號輸出一命中信號及一記憶體位址信號;俾藉由該等內容定址記憶單元之彼此串接,而使該樣式資料之長度為可變的。
For receiving an input data, a pattern data and a data clock signal and outputting a hit signal and an address signal, a content addressable memory includes a plurality of content addressable memory units connected in series, each content addressable memory unit being adapted to receive the input data and the data clock signal and to output a comparison result signal, and an encoder coupled to the comparison result signal of each content addressable memory unit and adapted for outputting a hit signal and a memory address signal subject to the comparison result signal received.
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聯繫方式 |
聯絡人:
研發處產學合作總中心 |
電話:
(02)3366-9949 |
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地 址:
10617臺北市大安區羅斯福路四段1號 禮賢樓六樓608室 |
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