 技術摘要： |
The invention discloses the variable attenuator with characteristics, comprising wide attenuation ranges; syntheses on group delays, and low variation of the group delay. The building blocks, which construct the variable attenuator, comprise internal matching networks, external matching networks, delay networks, protecting networks, biasing network, a power combining network, and variable impedance networks. The elements, which realize the internal matching networks, external matching networks, signal combining networks, comprise resistor, inductor, capacitor, and transmission lines. The elements, which realize the variable impedance networks, comprise n-channel field-effect transistor (FET), p-channel FET, n-type bipolar junction transistor (BJT), and p-type BJT. The elements of the variable attenuator can be either integrated on a semiconductor chip by using system-on-chip (SOC) technologies. The building blocks of the variable attenuator can be realized on different substrates and integrated in a module by using multi-chip module (MCM) technologies.
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聯繫方式 |
| 聯絡人：
研發處產學合作總中心 |
電話：
(02)3366-9949 |
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| 地 址：
10617臺北市大安區羅斯福路四段1號 禮賢樓六樓608室 |
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