 技術摘要： |
半導體記憶裝置包括具有閘極、源極及汲極之電晶體及金屬絕緣體半導體(MIS)結構。電晶體及MIS結構設置在共用基材上。MIS結構包括設置在半導體區域上之介電層、及電性設置在介電層上並耦接至電晶體之汲極的電極。電極包括塊部份及高電阻部份，兩者設置在介電層上。高電阻部份具有在自1.0×10 -4 Ωcm至1.0×10 4 Ωcm之範圍中的阻抗值或在自1.0×10 2 Ω/□至1.0×10 10 Ω/□之範圍中的片電阻值。
A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.0×10-4 Ωcm to 1.0 ×104 Ωcm or a sheet resistance in a range from 1.0 ×102 Ω/□ to 1.0×1010 Ω/□.
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聯繫方式 |
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