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應用於鎖相迴路系統之相位補償快速鎖定機制(鎖相迴路) / ( 分佈主動變壓式毫米波功率放大器電路 ) |
刊登日期:2014/05/21 |
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‧ 專利名稱 |
應用於鎖相迴路系統之相位補償快速鎖定機制(鎖相迴路) / ( 分佈主動變壓式毫米波功率放大器電路 ) |
‧ 專利證書號 |
I371923 8437441
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‧ 專利權人 |
國立臺灣大學 |
‧ 專利國家
(申請日) |
中華民國 (2009/01/21) 美國 (2009/07/20)
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‧ 發明人 |
林宗賢 , 邱威豪 , 黃昱翔 , |
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技術摘要: |
一種鎖相迴路,包括比較一參考時脈與一回饋時脈以產生一相位誤差訊號的相位頻率偵測器,一根據相位誤差訊號產生一電流訊號的充電泵,一判斷回饋時脈與參考時脈之間的相位誤差以產生一數位訊號的相位誤差類比/數位轉換器,一根據數位訊號產生一輔助電流訊號的輔助充電泵,一根據電流訊號及輔助電流訊號產生一電壓訊號的濾波器,一根據電壓訊號產生一輸出時脈的壓控振盪器,及一可變除數除頻器,其對輸出時脈除頻以產生該回饋時脈,並根據數位訊號改變其除數,使輸出之回饋時脈與參考時脈之間的相位誤差變小。
A phase locked loop includes a voltage controlled oscillator operable to generate an output signal corresponding to a reference signal in response to a control voltage signal outputted by a filter in response to a current signal, and a variable frequency divider operable to perform frequency division on the output signal using a variable divisor so as to generate a divided feedback signal. A charge pump outputs the current signal in response to a phase detecting output from a phase/frequency detector indicating phases of the divided feedback signal and the reference signal. A phase error comparator outputs, in accordance with the phase detecting output, a digital output indicating whether the divided feedback signal lags or leads the reference signal and further indicating a phase difference between the divided feedback signal and the reference signal. The variable frequency divider determines a value of the variable divisor in accordance with the digital output to reduce the phase difference between the divided feedback signal and the reference signal.
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聯繫方式 |
聯絡人:
研發處產學合作總中心 |
電話:
(02)3366-9949 |
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地 址:
10617臺北市大安區羅斯福路四段1號 禮賢樓六樓608室 |
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