加權平均線長模型
  ‧ 專利名稱 以加權平均導線長模型實現之解析配置演算法
  ‧ 專利證書號 I430127
8689164
  ‧ 專利權人 臺大
  ‧ 專利國家
    (申請日)
美國 (2011/10/18)
中華民國 (2011/11/30)
  ‧ 發明人 包偉力 , 徐孟楷 , 張耀文 ,
 
技術摘要:
本發明係一種用以產生積體電路中複數個元件佈局之電腦實現法,藉由使用一加權平均線長模型估算總線長以達成目標。藉由對一目標函數進行最佳化流程可決定此一佈局,該函數包括一由加權平均線長模型估算之線長函數。此法可進一步用於三維積體電路中複數個元件之佈局,此法同時考量矽穿孔之大小及其實體位置。由於矽穿孔之實體位置已於佈局時決定,三維繞線可輕易地在繞線長、矽穿孔數量及矽晶總面積等方面達到更佳之成果。

A computer-implemented method to generate a placement for a plurality of instances for an integrated circuit (IC) by utilizing a novel weighted-average (WA) wirelength model, which outperforms a well-known log-sum-exp wirelength model, to approximate the total wirelength. The placement is determined by performing an optimization process on an objective function which includes a wirelength function approximated by the WA wirelength model. The method can be extended to generate a placement for a plurality of instances for a three-dimensional (3D) integrated circuit (IC) which considers the sizes of through-silicon vias (TSVs) and the physical positions for TSV insertion. With the physical positions of TSVs determined during placement, 3D routing can easily be accomplished with better routed wirelength, TSV counts, and total silicon area.



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