用於提昇式離散小波轉換硬體實現之翻轉式演算法及其硬體架構
  ‧ 專利名稱 用於提昇式離散小波轉換硬體實現之翻轉式演算法及其硬體架構
  ‧ 專利證書號 200668
4012781
7076515
  ‧ 專利權人 國立臺灣大學
  ‧ 專利國家
    (申請日)
中華民國 (2002/07/12)
日本 (2002/08/07)
美國 (2002/08/16)
  ‧ 發明人 陳良基 , 黃朝宗 , 曾博志 ,
 
技術摘要:
本發明係揭露一種用於提昇式離散小波轉換硬體實現之翻轉式演算法及其硬體架構,其係以一般提昇式結構為出發點,將通過基本運算單元之間的乘法器之切集合上的邊全部乘以該乘法係數之倒數,藉此切斷時間延遲累積效應,然後再將該基本運算單元中的運算點分開成二個加法器,以利用翻轉式架構改善其臨界路徑太長之缺點,如此既可保有提昇式結構在硬體需求量方面的優勢,亦可大量縮短臨界路徑,以達到最佳的硬體架構。
A flipping algorithm for the hardware realization of Lifting-based DWT, relates a flipping algorithm and hardware architecture for the hardware realization of Lifting-based DWT, by using lifting architecture as starting point, by multiplying the edge of the cutset which is through the multiplier and the basic computing unit by the reciprocal of multiplier coefficient in order to cut off the accumulation effect of timing delay. And separating the computing node of said basic computing units into 2 adders then applying flipping architecture to shorten the critical path, therefore not only can keep the merits of Lifting Scheme in hardware requirement but also can shorten the critical path to achieve the optimized hardware architecture.




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