使用降低寄生電容效應技巧之毫米波壓控震盪器
  ‧ 專利名稱 電晶體壓控震盪器
  ‧ 專利證書號 I341087
US 7,671,689 B2
  ‧ 專利權人 國立臺灣大學
  ‧ 專利國家
    (申請日)
中華民國 (2007/11/15)
美國 (2008/03/14)
  ‧ 發明人 鄧平援 , 江簡富 ,
 
技術摘要:
一種電晶體壓控振盪器,本發明揭露之電晶體壓控振盪器,於原本一包含第一電晶體與第二電晶體之交叉耦合式電感電容槽(LC-tank)電晶體壓控振盪電路,搭配一包含第三電晶體與第四電晶體之電晶體倍頻電路。首先將第一閘極連接第二汲極,第二閘極連接第一汲極;復使第三源極連接第一源極,第四源極連接第二源極;最後將第三閘極連接第四閘極,第三汲極連接第四汲極。如此可使原本存在於第一電晶體之寄生電容與原本存在於第二電晶體之寄生電容透過電晶體倍頻電路產生類似電容串聯之效果。該電容串聯效果使本壓控振盪器之總電容值降低,以提升該壓控振盪電路之工作頻率,復使得電路得以操作於更高之頻率。
A FET transistor voltage-controlled oscillator is provided that includes a crossed-coupled inductor capacitor tank (LC-Tank) transistor voltage-controlled circuit having a first transistor and a second transistor, as well as a transistor frequency multiplying circuit having a third transistor and a fourth transistor. In the design, the gate of the first transistor is connected to the drain of the second transistor, and the gate of the second transistor is connected to the drain of the first transistor. Then, the source of the third transistor is connected to the source of the first transistor, and the source of the fourth transistor is connected to the source of the second transistor. Last, the gate of the third transistor is connected to the gate of the fourth transistor, and the drain of the third transistor is connected to the drain of the fourth transistor. Therefore, the parasitic capacitance present in the first transistor and the parasitic capacitance present in the second transistor generate an effect similar to two capacitors connected in series, via the transistor frequency multiplying circuit. The effect reduces the total capacitance of the voltage-controlled oscillator, to increase the working frequency of the voltage-controlled circuit and allow a circuit having the voltage-controlled circuit to operate at a high frequency.




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