時脈率減半之高速類比數位轉換器
  ‧ 專利名稱 時脈率減半之高速類比數位轉換器
  ‧ 專利證書號 I450500
US 7,872,601 B2
  ‧ 專利權人 國立臺灣大學
  ‧ 專利國家
    (申請日)
中華民國 (2009/01/17)
美國 (2009/04/02)
  ‧ 發明人 江簡富, 楊善詠,
 
技術摘要:
所揭露的是一種12位元70Msps(每秒取樣率)的管線式類比數位轉換器,其係應用管線式的結構技術,採二階四級電路串接的同步處理方式,每階含有二級電路,該二級電路共用一3位元快閃類比數位轉換器,亦即每一級電路於每一時脈期間產生一3位元訊號輸出,加以外部正反時脈同步觸發,每一階電路於每一正反時脈期間可產生6位元訊號輸出。因之,本管線式類比數位轉換器在每一個正反時脈的時間內共計可產生12位元訊號輸出。本發明除可提高轉換速度並縮短取樣轉換時間、降低消耗功率外,整體電路所佔晶片面積亦可大幅縮減。經由模擬結果顯示,本轉換器在�1.8V電源操作下,當取樣頻率為70Msps時,約消耗155.08毫瓦。

Disclosed is a designed and implemented 12-bit 70 Msps pipeline analog-to-digital converter. Two adjacent blocks operate at opposite clock phases to reduce the chip size and power consumption. Since the opposite clock phases are designed to be provided by external devices, the timing between these two clock phases must be accurate. Note that the architecture of pipeline ADC consists of four stages, divided into two groups, wherein two adjacent stages in each group share one 3-bit flash ADC, hence only two 3-bit flash ADCs are required in this scheme. Therefore, there are 6-bit signal produced from each 3-bit flash ADC within one clock phase which consists of two opposite clock phases. And within the same period, the total output of the pipeline analog-to-digital converter would be 12-bit. From the simulation results, when the sampling rate is 70 Msps, this converter consumes 155 mW (TBV) at a ±1.8 V supply.




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