用於移動估計的全域消除演算法及其硬體架構設計
  ‧ 專利名稱 用於移動估計的全域消除演算法及其硬體架構設計
  ‧ 專利證書號 177013
  ‧ 專利權人 國立臺灣大學
  ‧ 專利國家
    (申請日)
中華民國 (2002/04/12)
日本 (2002/06/06)
韓國 (2002/06/25)
美國 (2002/06/27)
  ‧ 發明人 陳良基, 黃毓文, 簡韶逸,
 
技術摘要:
本發明係提供一種用於移動估計的全域消除演算法及其硬體架構,其係將連續消除演算法中資料流的分支有效去除,使資料流更加順暢且適合硬體實現;且因每個移動向量之處理時間為固定者,初始猜測可以省略,搜尋位置的省略比率係不隨時間改變並可大幅提升。該全域消除演算法具有準確性高之搜尋結果,其結果大多與影像之平均品質為最佳的全搜尋區塊比對演算法相同,有時甚至具有更佳的峰值信號雜訊比,使得本發明其有很高的可靠度。全域消除演算法的硬體架構主要係由心脈式跳動模組、樹狀加法器及樹狀比較器所組成,與其它許多實現全搜尋區塊比對演算法的硬體架構比較,此硬體架構所使用每一邏輯閘的運算能力為最高,且在相同的移動向量生產率下邏輯閘所消耗的功率則最低。
A global elimination algorithm for motion estimation and the hardware architecture thereof that can efficiently remove the braches in the data flow, so that the data flow is smoothened and is more adapted for hardware implementation. Because the processing time for each motion vector is fixed, preliminary prediction can be eliminated. The elimination ratio of the search locations will not be varied with time change and thus can be increased. The global elimination algorithm can produce a search result of high accuracy that is identical to that of a full-search block matching algorithm. The peak signal-to-noise ratio of global elimination algorithm is at times better than that of full-search block matching algorithm. Compared with other architectures based on the full-search block matching algorithm, the hardware architecture of the present invention can provide a best computational capability for each logic gate, while the power consumption of logic gates is minimum under the same throughput of motion vector.




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