 技術摘要 / Our Technology： |
本案係提供一種全數位式鎖相迴路(ADPLL)，其包含一第一除頻器、一相位頻率偵測器(PFD)、一控制單元、一數位控制振盪器(DCO)及一第二除頻器。該第一除頻器將一回授之時序信號的頻率降頻為1/M輸出一輸出信號，該PFD依據一參考時脈信號及該輸出信號之相位與頻率的差異輸出一dn及一up信號，接著，於四個工作模式期間，該控制單元執行二元搜尋演算法(Binary Search)並依據來自PFD之up、dn信號之數值及乘數因子而設定範圍控制DCO之輸出頻率，且該第二除頻器接收此輸出頻率及根據來自該控制單元之多個數位控制信號之一位元數進行除頻而輸出一作為回授信號至該第一除頻器。
An all-digital phase-locked loop (ADPLL) composed of digital circuits is provided. The ADPLL includes a phase-frequency detector (PFD), a control unit, a digital controlled oscillator (DCO), and a plurality of frequency dividers. A first frequency divider divides a frequency of a feedback signal CKOUT by a natural number M to generate a first output signal CKOUT/M. The PFD generates a decrement signal dn and an increment signal up, based on a phase difference and a frequency between a first reference clock signal CKIN and the first output signal CKOUT/M. The DCO generates a clock signal CKDCO based on the digital control signals. A second frequency divider receives the digital control signals from the control unit and the CKDCO from the DCO and divides the frequency of the CKDCO by a bit number of the digital control signals to generate a feedback signal CKOUT to the first frequency divider.
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| 專利簡述 / Intellectual Properties： |
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聯繫方式 / Contact： |
| 臺大產學合作總中心 / Center of Industry-Academia Collaboration, NTU |
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| Email：ordiac@ntu.edu.tw |
電話/Tel：02-3366-9945 |
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