Methods for QDI circuit minimization
刊登日期:2017/02/21
  ‧ 專利名稱
  ‧ 專利證書號 10496773B2
9576094B2
  ‧ 專利權人 國立臺灣大學
  ‧ 專利國家
    (申請日)
美國 (2014/08/20)
美國 (2017/01/06)
美國 (2019/12/02)
 
  ‧ 發明人/PI 江介宏
  ‧ 單位 台積電-臺灣大學聯合研發中心
  ‧ 簡歷/Experience
技術摘要 / Our Technology:
A logic circuit includes first and second input, an output, an input acknowledgement node, an output acknowledgement node, a logic evaluation block, a pre-charging circuit, and a completion detection circuit. The logic evaluation block performs a logic evaluation of first and second input signals at the first and second inputs, and to output an output signal corresponding to the logic evaluation. The pre-charging circuit pre-charges the logic evaluation block in response to the first input signal and an acknowledgement signal at the input acknowledgement node. The completion detection circuit generates an acknowledgement signal at the output acknowledgement node in response to the second input signal and the output signal.



專利簡述 / Intellectual Properties:




 

聯繫方式 / Contact:
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