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 Probabilistic framework for compiler optimization with multithread power-gating controls
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刊登日期：2021/09/07 |
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| ‧ 專利名稱 |
Probabilistic framework for compiler optimization with multithread power-gating controls |
| ‧ 專利證書號 |
11112845B2
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| ‧ 專利權人 |
國立臺灣大學 |
‧ 專利國家
(申請日) |
美國 (2015/12/10)
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| ‧ 發明人/PI |
李政崑,
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| ‧ 單位 |
聯發科技-臺大創新研究中心
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| ‧ 簡歷/Experience |
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| 技術摘要 / Our Technology： |
A probabilistic framework for compiler optimization with multithread power-gating controls includes scheduling all thread fragments of a multithread computer code with the estimated execution time, logging all time stamps of events, and sorting and unifying the logged time stamps. Time slices are constructed using adjacent time stamps of each thread fragment. A power-gating time having a component turned off for each time slice is determined. Power-gateable windows that reduce energy consumption of the time slice is determined according to the power-gating time. The compiler inserts predicated power-gating instructions at locations corresponding to the selected power-gateable windows into the power-gateable computer code.
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| 專利簡述 / Intellectual Properties： |
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聯繫方式 / Contact： |
| 臺大產學合作總中心 / Center of Industry-Academia Collaboration, NTU |
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| Email：ordiac@ntu.edu.tw |
電話/Tel：02-3366-9945 |
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