 技術摘要 / Our Technology： |
一種時鐘樹結構合成方法，可應用於積體電路或者印刷電路板之實體設計中以形成對稱的時鐘樹結構，同時達到將時鐘歪斜最小化、具製程變異容忍度以及加快合成速度之效果。於本發明中，為了避免某層次之分枝數過多造成時鐘樹結構不符合扇出限制，藉由設置複數個假標的使得總標的數量進行因式分解之結果能夠符合扇出限制，同時亦可藉由採用蛇行繞線，使得該時鐘樹結構的各個層次之分枝長度皆相等，而達到對稱的時鐘樹結構設計，降低時鐘樹之時鐘歪斜。
A method for synthesizing a clock-tree structure may be applied to a physical design such as an integrated circuit or a printed circuit board to form a symmetric clock-tree structure, while achieving the effect including minimizing a clock skew, having a process variability tolerance and increasing the synthesizing rate. In the present invention, in order to prevent the number of branches in a certain level from being too large to cause the clock-tree structure not to satisfy the fan-out limit, the result of factoring the number of the total targets may be satisfied the fan-out limit by providing a plurality of false targets. At the same time, the branch length of each level in the clock-tree structure may be equal by employing serpentine winding, so as to achieve a symmetric clock-tree structure design and reduce the clock skew of the clock-tree.
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| 專利簡述 / Intellectual Properties： |
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聯繫方式 / Contact： |
| 臺大產學合作總中心 / Center of Industry-Academia Collaboration, NTU |
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| Email：ordiac@ntu.edu.tw |
電話/Tel：02-3366-9945 |
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專利行銷平台