Simultaneous Layout Migration and Decompossition for Double Pattering Technogy
  ‧ 專利名稱
  ‧ 專利證書號
  ‧ 專利權人 國立臺灣大學
  ‧ 專利國家
    (申請日)
中華民國 (2009/07/02)
美國 (2009/08/31)
 
  ‧ 發明人/PI 張耀文 ,許欽雄,
  ‧ 單位 電子工程學研究所
  ‧ 簡歷/Experience
技術摘要 / Our Technology:
一種積體電路同時佈局遷移和分解之方法,其係應用於雙圖案徹影技術中,對初始佈局圖案之次圖案進行切割處理而建構具有獨立段或分割段之潛在性衝突圖;對該潛在性衝突圖移除奇數連結循環以對該獨立段或分割段進行切割處理;依據切割處理後所得到的各分段與相鄰分段間的相對位置關係以建構雙圖案考量約束圖;以及根據該雙圖案考量約束圖對切割處理後所得到的各分段指定為第一色層或第二色層,以得到最終佈局圖案。木發明可藉由同時實施佈局遷移和佈局分解以避免分別以不同順序對初始佈局圖案實施佈局遷移和佈局分解可能造成所產生的佈局圖案具有較大的佈局面積、存在有較多圖案衝突或圖案縫合之情形。

A method for concurrent migration and decomposition of an integrated circuit layout applicable to double patterning lithography techniques is provided. The method includes cutting a sub-pattern of an initial pattern to configure a potentially conflicting pattern having separate or cutting sections; removing odd cycles in the potential conflicting pattern so as to cut the separate or cutting sections; configuring the double patterning constraint based upon corresponding location relations between each and adjacent cut sections; and assigning a first color layer or a second color layer to the cut sections according to the double patterning constraint to obtain a final layout pattern. Therefore, disadvantageous factors and patterning conflicts caused by separate processes as encountered in the prior art are avoided.



專利簡述 / Intellectual Properties:




 

聯繫方式 / Contact:
臺大產學合作總中心 / Center of Industry-Academia Collaboration, NTU
Email:ordiac@ntu.edu.tw 電話/Tel:02-3366-9945