Zero-Conflict Layout Decomposition for Double-Patterening Technology
刊登日期:2014/05/21
  ‧ 專利名稱 應用於雙圖案微影技術的佈局分解方法
  ‧ 專利證書號 I397828
  ‧ 專利權人 國立臺灣大學
  ‧ 專利國家
    (申請日)
中華民國 (2009/07/06)
美國 (2010/07/02)
 
  ‧ 發明人/PI 張耀文 ,陳皇宇 ,
  ‧ 單位 電子工程學研究所
  ‧ 簡歷/Experience
技術摘要 / Our Technology:
A layout decomposition method, applicable to a double pattern lithography, includes the steps of: putting at least a stitch on each of a plurality of sub-patterns of an initial layout pattern at preset intervals to thereby divide the each of the plurality of sub-patterns into a plurality of unit blocks each selectively labeled as a first region or a second region such that the first region and the second region in same said sub-pattern alternate, wherein any two neighboring ones of said unit blocks attributed to any two neighboring ones of said sub-patterns, respectively, are labeled as the first region and the second region, respectively; reducing the stitches of any two neighboring ones of said unit blocks attributed to any two neighboring ones of said sub-patterns, respectively, so as to generate a first layout pattern having a minimum number of stitches; and reducing the stitches of any two contiguous ones of said unit blocks of each of said sub-patterns in the first layout pattern, so as to generate a second layout pattern having a minimum number of stitches.



專利簡述 / Intellectual Properties:




 

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