基於對數可調式晶片網路之多核心處理器架構
刊登日期:2014/05/21
  ‧ 專利名稱 基於對數可調式晶片網路之多核心處理器架構
  ‧ 專利證書號 9111151
  ‧ 專利權人 臺大
  ‧ 專利國家
    (申請日)
美國 (2012/02/17)
美國 (2012/08/30)
 
  ‧ 發明人/PI 陳良基,蔡雋永,
  ‧ 單位 電子工程學研究所
  ‧ 簡歷/Experience
技術摘要 / Our Technology:
An exemplary embodiment of the present disclosure illustrates a network on chip processor including multiple cores and a Kautz NoC. Each of the cores is assigned with an addressing string with L based-D words, and the addressing string does not have two neighboring identical words, wherein L present of an addressing string length is an integer larger than 1, D present of a word selection is an integer larger than 2. Each of the cores is unidirectionally link to other (D-1) cores through the Kautz NoC, and in the two connected cores, the last (L-1) words associated with the addressing string of one core are same as the first (L-1) words associated with the addressing string of the other core.



專利簡述 / Intellectual Properties:




 

聯繫方式 / Contact:
臺大產學合作總中心 / Center of Industry-Academia Collaboration, NTU
Email:ordiac@ntu.edu.tw 電話/Tel:02-3366-9945